As MOSFET and CMOS device characteristic sizes are scaled below 0.13 microns including below 0.1 micron, the process window for wet and dry etching processes are increasingly difficult to control to achieve desired critical dimensions. For example, in forming dielectric offset spacers, also referred to as sidewall spacers, the required width of the offset spacer is increasingly smaller. For example, the width of the offset spacer may be as small as 100 Angstroms (10 nanometers) or less in 65 nanometer characteristic dimensioned CMOS devices.
The offset spacer dielectric is formed adjacent either side of the gate structure and serves to allow the formation of source/drain extensions (SDE) whereby a relatively lower amount of N or P-type doping is first formed in the semiconductor substrate adjacent the gate structure by ion implantation prior to forming the offset spacers which then act as an ion implant mask for forming higher doped regions adjacent the offset spacers.
As device characteristic dimensions shrink below about 0.13 microns, achieving close dimensional tolerances of offset spacers is critical to achieving reliable electric performance and avoiding short channel effects (SCE). For example, SDE regions affect SCE according to both depth and width of the SDE doped region. The width of the offset spacers determines at least the width of the SDE regions. Offset spacer formation typically requires both deposition and etching processes, for example, to first deposit and subsequently remove portions of deposited dielectric layers. As device sizes decrease below about 0.13 microns both the deposition process and the etching process have extremely narrow process windows whereby dimensional variation undesirably alters CD's and electrical performance of the CMOS device. For example, in 65 nanometer technologies, an offset spacer width may be as small as 50 Angstroms, making a variation in width of the offset spacer of 2-4 nm a variation of 40 to 80%. In addition, typical methods of measuring CD's such as SEM and TEM may make variation of a few nanometers difficult to accurately detect. Moreover, such a variation in offset spacer dielectric layer thickness or offset spacer will likely undesirably affect SDE formation thereby degrading electrical performance of the CMOS device including increasing SCE.
There is therefore a need in the semiconductor integrated circuit manufacturing art for an improved method for dielectric offset spacer formation to achieve a greater degree of precision in CD control thereby improving the electrical operating performance and reliability of CMOS devices.
It is therefore among the objects of the present invention to provide an improved method for dielectric offset spacer formation to achieve a greater degree of precision in CD control thereby improving the electrical operating performance and reliability of CMOS devices, in addition to overcoming other shortcomings of the prior art.